A twist pin is an elongated electrical conductor formed from multiple helically coiled strands of wire. At least one longitudinal segment of the coiled strands is untwisted in an anti-helical direction to expand the strands into a resilient bulge. The bulge has a larger diameter than the diameter of the regularly stranded wires of the adjacent portions of the twist pin on the opposite ends of the bulge. The strands of wire are preferably formed from beryllium copper or other electrically conductive material having the necessary stiffness and resiliency to permit the bulge to compress while the regularly twisted strands in the adjacent portions of the twist pin remain substantially unaffected.
Twist pins have been used to interconnect and conduct electrical signals between vertically stacked and spaced apart printed circuit boards. The twist pins are inserted through aligned plated through holes or “vias” in the vertically stacked circuit boards with the bulges contacting the conductive sidewalls of the vias. Conventional traces on the printed circuit boards, which connect to the vias, conduct signals to and from the twist pins in the vias. If the signal is not to be conducted from the via to the twist pin, a bulge is not formed in the twist pin at the location where the twist pin which extends through that via, or the via is not electrically connected to other components of the printed circuit board. In addition to electrically interconnecting the stack of printed circuit boards, the twist pins also assist in mechanically holding the stack of printed circuit boards together. Because of their vertical connection capability between the stacked printed circuit boards, twist pins are sometimes referred to as “z-axis” interconnectors. Twist pins and their uses are described in U.S. Pat. Nos. 5,014,419, 5,054,192, 5,112,232, 6,584,677, 6,716,038, 6,729,026 and 6,971,415, among others.
Although twist pins have been successfully used as z-axis interconnectors, it is believed that twist pins have not been used in interconnection interfaces for testing high performance integrated circuits, such as microprocessors or memory chips, or for docking electronic components by direct connection to contact pads or surfaces.
Integrated circuits (ICs) are active functional building blocks for most electronic products. Integrated circuits typically contain hundreds of thousands or millions of individual transistors which are connected together to perform sophisticated and complex functions. These integrated circuits, commonly referred to as “chips,” are built up as multi-layer structures using complicated and lengthy manufacturing processes. Small contact surfaces or areas called “pads” are formed on the outside of the chip to conduct electrical power to operate the transistors, to apply input signals to stimulate the transistors, and to deliver output signals created by operation of the transistors in response to the input signals.
Due to their highly integrated nature, most modern integrated circuits have many closely spaced contact pads distributed around the periphery of a chip. The chip may have dimensions of less than 0.5 inches on a side, and ten or more contact pads may be formed along each of the four sides of the chip. Normally, fine lead wires, called “leads,” are microscopically bonded to each of the contact pads, and the leads are extended from the chip to larger electrical terminals on a much larger plastic housing within which the chip is permanently retained. The plastic housing with its interiorly-confined chip and larger exterior electrical terminals is referred to as a “package” or sometimes simply as an electronic “device.” The exterior electrical terminals of the package are spaced further apart and can be more easily contacted mechanically and electrically by conductor traces on a printed circuit board or by other conductors. In some cases the packages are connected to sockets which have a capability to both electrically contact the terminals and hold the package in place, or the electrical terminals of the package are soldered or adhered directly to conductor traces of the printed circuit board.
Because of the complexity of the integrated circuit manufacturing process and the microscopic size of a large number of electronic components which must be integrated into the single chip in a properly functional and interrelated manner, there is a significant risk that a new chip is defective because of discrepancies which occurred during the manufacturing process. For this reason, it is typical that each batch or run of integrated circuits will achieve less than a 100% yield of properly functional chips. Consequently, newly manufactured chips are subjected to various levels of functional tests to identify those that are defective. By identifying defective chips before they are encapsulated in the packages, the cost of manufacturing fully functional electronic components is reduced, since additional costs are not incurred in encapsulating defective chips in packages. Various functional tests, including real-time complete functionality tests at the chip level, are performed whenever economically possible to eliminate the defective chips before they are encapsulated in packages.
Chip level testing is difficult because of the high density of closely-spaced small contact pads on the chip. To test the chip, electrical contact must be made with a significant number of the contact pads. If the chip is to be completely functionally tested, electrical contacts must be made with all of the contact pads. The close spacing or “pitch” of the contact pads has made it difficult or impossible to establish electrical contact with each of the large number of closely pitched contact pads on a rapidly-occurring, cost-efficient and easily-replicated basis. Making electrical contact with the contact pads on a rapidly-occurring, cost-efficient and easily-replicated basis is necessary if the chip is to be tested economically. Electrical test probes cannot quickly and reliably contact to the contact pads, because such probes usually consume more space than the pitch between the densely positioned contact pads. Even if space is available, significant operator attention is required to properly position the probes. For these and other reasons, some chip manufacturers usually do not perform functional tests which confirm the full functionality of the chip, but instead rely on partial functional tests which can be more easily and economically performed by making probe contact with less than all of the contact pads. Of course, using less than a complete functional tests to evaluate a chip increases the risk that the chip will be determined at a later time to be defective in some regard, thereby increasing manufacturing costs due to packaging a partially defective chip and assembling an electronic product using a package with the partially defective chip.
Making good electrical contact of the probes with the contact pads is further complicated because the chip manufacturing process typically results in contact surfaces on the contact pads which are not located in the same plane. The chip manufacturing process builds up multiple layers and components on top of one another by using layer deposition techniques. Since the layers and the components do not necessarily build up evenly and uniformly, it becomes impossible to assure that all of the contact pads on the chip are built up to the same height. Consequently, the surfaces of the contact pads are usually at slightly different relative heights.
Variations in vertical height of the contact pads relative to one another requires that each of the contact probes have the ability to move vertically relative to the other adjoining probes. Vertical movement capability assures that each probe will make firm conductive contact with the contact pad, thereby assuring good signal conductivity between the probe and the contact pad. Insufficient contact results in an unreliable electrical path for communicating signals. An unreliable electrical path may falsely indicate that a chip is functioning incorrectly, when in reality the discrepancy is from the electrical contact with the contact pad and not from the functionality of the chip itself.
Ideally, the force that each probe should exert on a contact pad should be in the range of 1-15 grams, and preferably in the range of 9-15 grams. Usually a contact force of less than 9 grams per contact will not assure an effective signal path. To assure this amount of force on a large number of non-coplanarly located contact pad surfaces, it becomes necessary to force the probes into more forceful contact with the higher-level contact pads compared to the lesser force of the probes on the lower-level contact pads, to assure that all the probes contact all of the pads with adequate force. The relatively small contact force per probe multiplies into a considerable total force on the chip when many contact pads are involved. Such force may be sufficient to crack or otherwise fracture a chip.
The other practical requirement for testing chips is that each of the chips must be tested relatively quickly, in order to achieve mass testing. For the same reasons that full functional testing is superior to partial functional testing, it is desirable to test all of the newly-manufactured chips, rather than do selective testing of less than the entire batch of newly-manufactured chips. Convenience and cost-efficiency in establishing reliable electrical connections is therefore paramount in order to test large numbers of chips.
The convenience, efficiency, force requirements, density and placement considerations for making electrical contact with the contact pads must be taken into account when making interconnect interfaces for the chips. Such interconnect interfaces are sometimes referred to as “test sockets.” Test sockets are used to apply electrical power and input signals to a chip or to some other electronic unit under test and to receive output response signals from the chip or unit under test. An exemplary test socket is described in U.S. Pat. No. 6,512,389, among others. Fixtures used with test sockets to test chips are described in U.S. Pat. Nos. 6,127,835, 6,175,243 and 6,292,004, among others.
One of the most advanced test sockets utilizes spring probes, and is described in U.S. Pat. No. 6,512,389. A spring probe is an electrically-conductive, resilient mechanical structure which has the ability to longitudinally adjust its length, usually by slight compression. Spring probes have a variety of different configurations. Each spring probe is retained in an aperture which has been drilled or otherwise formed in a support structure or plate. The apertures are formed in locations which are aligned with the contact pads of the chip to be tested. At least one end of each spring probe projects beyond the support plate. A fixture supports the chip and brings it into adjacency with the support plate while aligning and contacting the projecting tip ends of the spring probes with the contact pads of the chip. Electrical power, input test signals and output response signals are conducted to and from the chip through the spring probes. Electrical conductors connect to the spring probes in order to supply and receive the electrical power and signals. The longitudinal compressibility of each spring probe assures that it will make contact with the variable-height and non-coplanarly-located contact pads. The apertures in the support plate retain the spring probes to assure their registration with the contact pads.
Despite the advantages of spring probe test sockets, they present certain limitations. One limitation involves the physical size of the spring probe itself. Although there are many different configurations of spring probes, all of them generally have a cross-sectional width which is comparable to or greater than the spacing or pitch between the most densely located contact pads on modern chips. Consequently in most modern chips, it becomes impossible to position the spring probes close enough to each other to achieve registration with the contact pads on the chip while still retaining the spring probes in the desired position in the support plate. Consequently, the use of spring probes during testing of modern chips is usually limited to partial functionality tests, since electrical contact with all of the contact pads is not possible.
Another limitation of spring probe test sockets is that each individual spring probe applies a different force to the contact pads according to the degree of compression of each spring probe. The variations in contact force result from the different, non-coplanar levels of the contact pads and variations in the spring coefficients of each spring probe. Variations in contact force have the potential to create sufficient force differentials over the surface of the chip which could cause the chip to fracture or crack before or after the chip is encapsulated in the package. A fracture or crack in the chip could also break the bond of a lead to the contact pad.
Another significant limitation on spring probe test sockets is that spring probes degrade the quality of input test signals supplied to the chip and the quality of the output response signals supplied from the chip, particularly at the very high frequencies at which many modern integrated circuits operate. For example, modern microprocessors operate at switching frequencies in the neighborhood of 3-20 Ghz, and it is expected that the switching speeds will increase even more in the future. At such high frequencies, the quality of the signal path and the environment surrounding the signal path have the potential to create significant influences over the quality of the signals conducted.
The characteristics and quality of the signals conducted by spring probes are influenced by a change of inductance resulting from the variations in length of the spring probes when compressed against the contact pads. The variation in length changes the effective length of the signal path and the impedance of the signal path. The variation in length also changes the characteristics of the electrical field which surrounds the spring probe when it conducts current. The electromagnetic radiation of the electrical field from one spring probe influences the signals conducted by adjoining spring probes, in a manner sometimes referred to as “cross-talk.” Variable field effects from one chip to the next makes it difficult or impossible to eliminate the effects of cross-talk on the output response signals. The variable effects also alter the phase relationship between the input and output signals. Variations in phase relationship become extremely significant in determining proper functionality at the high switching frequencies commonly used in modern chips. Proper testing depends on reliably evaluating those phase relationships.
Since effective testing and use of modern chips depends heavily on the quality and phase relationships of the signals applied to and received from those chips, it is very important to minimize individual signal anomalies in a high-performance, reliable, rapid and cost-efficient interconnect interface, used both for chip testing and for more permanent docking of chips in electronic products.